The present invention relates generally to programmable logic devices, and more particularly to nonvolatile memory cells for use in programmable logic devices.
Programmable logic has increasingly become a valued resource for system designers. Programmable logic can allow for a custom logic design to be implemented without the initial cost, delay and complexity of designing and fabricating an application specific integrated circuit (ASIC).
Currently, there are many variations of programmable logic, including simple programmable logic devices (SPLDs), complex PLDs (CPLDs), and field programmable gate arrays (FPGAs). Such devices typically include logic circuits and corresponding memory circuits. The particular function of a logic circuit can be determined according to data stored in a corresponding memory circuit. Some programmable logic arrangements can include switching circuits (also called programmable interconnects) that enable and/or disable switching paths according to data stored in a memory circuit.
A programmable logic memory circuit may be volatile or non-volatile. One particular example of a volatile memory circuit can be a static random access memory (SRAM) cell. A drawback to volatile approaches is that an ancillary non-volatile memory (such as a programmable read only memory (PROM)) is usually necessary. Upon power-up, data from a PROM can be loaded into SRAM cells of a programmable logic device. An advantage of volatile programmable logic can be the increased speed of such devices and/or a simpler manufacturing process technology. A disadvantage can be the volatile nature of such devices. A power-up/loading step, such as that described above, can introduce more delay into the startup operation of a device. Further, the addition of an ancillary non-volatile memory device may increase size and/or cost.
Non-volatile programmable logic typically does not require a power-up loading step. Currently, there are a number of approaches to forming non-volatile programmable logic. Such approaches may generally be categorized as xe2x80x9cone time programmablexe2x80x9d (OTP) or xe2x80x9cin system programmablexe2x80x9d (ISP). OTP devices may include approaches that use fuses, anti-fuses and/or electrically erasable read only memories (EPROMs). For the most part, once OTP devices are programmed, their functionality may not be changed. (EPROM based devices may include ultra-violet light windows for erasing, but typically at a prohibitively high increase in packaging cost).
In contrast to OTP devices, ISP devices may be reprogrammed. This can be a particularly valuable feature as designs may go through prototyping and/or revisions. Some ISP devices may be reprogrammed even after being soldered or otherwise connected to a circuit board. ISP devices may include programmable non-volatile memory devices such as electrically erasable and programmable read-only-memories (EEPROMs), including xe2x80x9cflashxe2x80x9d EEPROMs (which can allow for the rapid simultaneous erasure of multiple memory cells).
EEPROM structures (including flash EEPROM structures) typically utilize a floating gate that may be programmed and/or erased by placing charge on the floating gate. Various charge transport mechanisms can be utilized, including Fowler-Nordheim tunneling and/or channel hot electron injection, to name two examples.
Regardless of the particular programmable logic circuit structure employed, an increasing concern with programmable logic can be the operating speed and the power supply level requirement of such devices. An operating speed is typically the time required for applied input signals to generate corresponding output signals. Many aspects of a programmable logic design can impact operating speed. One aspect can include the speed at which memory cell data can be read. At the same time system speeds are increasing, the operating voltages of such systems are falling. Lower operating voltages may typically translate into lower operating speeds. For these and other reasons, it would be desirable to arrive at some way of increasing operating speed to compensate for speed reductions introduced by lower operating voltages.
Having described the general operation and variations of programmable logic devices, a particular conventional programmable logic memory cell will now be described. Referring now to FIG. 3, a conventional electrically erasable programmable logic device (EEPLD) cell is illustrated in a top plan view and designated by the general reference character 300. An EEPLD cell 300 may be conceptualized as including a cell boundary 302. A cell boundary 302 may define the limits of a repeatable structure within an integrated circuit. A mirror image repetition may be advantageous if contact sharing between adjacent cells is desirable.
A conventional EEPLD 300 may further include a first semiconductor region 304 and a second semiconductor region 306. First and second semiconductor regions (304 and 306) may include diffusions regions formed in a semiconductor substrate. Such diffusion regions may be formed by ion implantation or other conventional methods. First and second semiconductor regions (304 and 306) may be bounded by isolation structures (not shown) such as those formed by LOCOS (local oxidation of silicon) or STI (shallow trench isolation), or gate structures, as will be described below.
A conventional EEPLD 300 may further include a select gate 308 and a floating gate 310 situated between a first and second semiconductor region (304 and 306). The conductivity between a first and second semiconductor region (304 and 306) may be controlled by the particular state of a select gate 308 and floating gate 310. More particularly, a floating gate 310 may be programmed or erased, and thereby enable conductivity between the first and second semiconductor regions (304 and 306). In addition, a select gate 308 may be driven between a select and de-select potential and thereby enable conductivity between the first and second semiconductor regions.
Thus, when the select gate 308 is at a de-select potential, a relatively high impedance can exist between first and second semiconductor regions (304 and 306). However, when a select gate 308 is at a select potential, the impedance between first and second semiconductor regions (304 and 306) may depend upon a floating gate 310. If a floating gate 310 is in one state (e.g., erased) a relatively high impedance can exist between first and second semiconductor regions (304 and 306). If a floating gate 310 is in another state (e.g., programmed) a relatively low impedance can exist between first and second semiconductor regions (304 and 306).
An alternate way of conceptualizing the conventional approach shown in FIG. 3 is to consider a controllable current path Isense as existing between a first and a second semiconductor portion (304 and 306). The conductivity of the current path Isense may be controlled by a select gate 308 and a floating gate 310. FIG. 4 shows a side cross-sectional view taken along line 4xe2x80x944 to illustrate such a current path Isense. It is understood that by reversing a voltage applied between a first and a second semiconductor portion (304 and 306), the direction of a current path Isense may be reversed.
In the example of FIG. 3, a first semiconductor region 304 may include a first sense contact 312 that may be connected to a sense amplifier (not shown). Similarly, a second semiconductor region 306 can include a second sense contact 314 that may also be connected to a sense amplifier. A select gate 308 may include a select contact 316 that can be connected to a select line (not shown). In this way, a select line can be activated to provide memory data to a sense amplifier. A sense amplifier can amplify this information and use such information to establish the functionality of one or more logic circuits in a PLD.
A conventional EEPLD cell 300 may also include a programming portion 318 and a charge storage portion 320. A programming portion 318 may include circuit structures that establish the state of a floating gate 310. The particular programming portion 318 of FIG. 3 includes a programming node 322, a programming gate 324, and a tunneling region 326. A programming node 322 may receive a programming voltage that is relatively high in magnitude with respect to the power supply voltage of a PLD. A programming gate 324 may pass a programming voltage to a tunneling region 326. A tunneling region 326, when driven to a positive programming voltage, may allow electrons to tunnel through a tunneling dielectric from a floating gate 310, thereby establishing a low or negative threshold voltage for a floating gate 310. A low or negative threshold voltage may place a floating gate in a conducting state.
A floating gate 310 may also be placed into a non-conducting state by establishing a high threshold voltage. A positive erasure voltage may be applied to an erase node 330. An erasure voltage may be capacitively coupled to coupling capacitor portion 320. When an erasure voltage is sufficiently high, electrons may tunnel back through tunneling regions 326.
It is noted that coupling capacitor portion 320 can be relatively large to provide a larger capacitive coupling ratio between a capacitor formed at the tunneling region 326, and a capacitor formed between erase node 330 and coupling capacitor portion 320. A higher capacitive coupling ratio can speed erase and program operations.
It is noted that a limiting factor in EEPLD cell sizes can be a programming portion 318. As noted above, a programming portion 318 may have to supply a relatively high programming voltage. To enable such a function, a programming portion 318 may include high voltage structures for carrying such a programming voltage. Such structures may include particular diffusion schemes and/or isolation structures. Consequently, there may be a minimum spacing requirement between a programming portion 318 and adjacent circuit structures.
While the above-described conventional EEPLD cell can provide adequate functionality at particular speeds, there is a need for an even faster EEPLD cell for the various reasons described above.
One approach to increasing the speed of a cell such as that shown in FIG. 3, could be to increase the overall size of a select transistor 310. Such an approach can increase the overall size of a resulting PLD. This is undesirable as it may lead to increased manufacturing cost. Further, increasing a select transistor size may increase parasitic junction capacitance along the current path Isense. This may result in slower performance.
The present invention includes an electrically erasable and programmable logic device (EEPLD) cell that may provide higher read currents than conventional approaches. Unlike conventional approaches that include a single read current path, the present invention can provide multiple read current paths.
According to one embodiment, multiple read current paths may be provided by including a folded floating gate and folded select gate. In such an arrangement, the conductivity of a first current path may be controlled by a first portion of a floating gate and a first portion of a select gate. In addition, the conductivity of a second current path may be controlled by a second portion of a floating gate and a second portion of a select gate. Multiple current paths may result in larger read current and hence faster circuit operation.
According to one aspect of the invention, first select gate portions may be parallel to first floating gate portions. Such an arrangement may allow such structures to be separated form one another by a minimum process feature size, or a feature size smaller than conventional spacing used for EEPLD logic circuits or the like.
According to another aspect of the invention, to allow for a more compact structure, a select gate and/or a floating gate may have a gate length that is less than the gate lengths of conventional transistors, such as those used to form logic circuits in an EEPLD.
According to another aspect of the invention, current paths may include diffusion regions associated with the select gate and/or floating gate portions. A lateral diffusion of such diffusion regions may be less than that of conventional transistor sources and drains, such as those transistors used to form logic circuits in an EEPLD. Such an approach may also produce a more compact structure.
According to another aspect of the invention, each current path may include a select gate portion that is electrically in series with a corresponding floating gate portion. Thus, a select gate portion and corresponding floating gate portion can be in predetermined states to provide a low impedance current path.
According to another aspect of the invention, a select gate may be disposed over a select gate insulator and a floating gate may be disposed over a floating gate insulator that is greater than a select gate insulator. Such an arrangement can provide for rapid select gate operation while at the same time maintaining charge storage characteristics in a floating gate.